漢德百科全書 | 汉德百科全书
IT-Times
Mainframe
***Metaverse*ACM Turing Award*Banking and financial services*IDE*IT security and data protection policy*Government3D-DruckAndroidAR/VRArtificial IntelligenceBig DataBlockchainCAD/CAE/CAM/EDA/PDM/PLMChat/Video Conferencing/PhoneCloud ComputingCMSCNCComputer Algebra System and MathematicsCRM/EAM/ERP/SRM/SCM/HCM/QM/XM/WFMCross platformData analysisDatabase management systemsPrinter/Photocopier/ScannereBookeCommercePower Engineering SoftwareDriver assistance systemsFPGAGames industryGaming ClubGraphics software and graphics tabletGraphics card/Video cardSemiconductor technologyHPCICIndustrial RobotInstant Messaging und VoIPInternet of ThingsLinux/UnixMainframeMCU MedicineMicrosoft WindowsMobile Networks Modernization of agricultureMotherboardMusic productionOperating SystemPayment SystemPCI-SIGPLC/DCS/FCS/SCADA/MES Precision Instrument/Medical Equipment/Research EquipmentProduction Engineering/Manufacturing TechnologiesProfessional media softwareProgramming language and frameworkQuantum ComputingRoot name serverSensorSmart phoneSocial networkStreaming MediaStream processorSearch Engine TCP/IP ProtocolsTuring AwardProcessing Units - CPU, GPU, APU, TPU, VPU, FPGA, QPU, IPU, PICVersion controlDistributed systemVirtualization
IT-Times
Technology node 7 nm
Launched 2021 Designed by IBM Performance Max. CPU clock rate >5 GHz Cache L2 cache 32 MB per core Architecture and classification Technology node 7 nm Instruction set z/Architecture Physical specifications Cores 8
IBM z14
Launched 2017 Designed by IBM Common manufacturer(s) GlobalFoundries Performance Max. CPU clock rate 5.2 GHz Cache L1 cache 128 KB instruction 128 KB data per core L2 cache 2 MB instruction 4 MB data per core L3 cache 128 MB shared Architecture and classification Technology node 14 nm Instruction set z/Architecture Physical specifications Cores 10
IBM z15
Launched 2019 Designed by IBM Performance Max. CPU clock rate 5.2 GHz Cache L1 cache 128 KB instruction128 KB dataper core L2 cache 4 MB instruction4 MB dataper core L3 cache 256 MBshared Architecture and classification Technology node 14 nm Instruction set z/Architecture Physical specifications Cores 12
