Deutsch-Chinesische Enzyklopädie, 德汉百科
IT-Times
IC
***Metaverse*ACM Turing Award*Banking and financial services*IDE*IT security and data protection policy*Government3D-DruckAndroidAR/VRArtificial IntelligenceBig DataBlockchainCAD/CAE/CAM/EDA/PDM/PLMChat/Video Conferencing/PhoneCloud ComputingCMSCNCComputer Algebra System and MathematicsCRM/EAM/ERP/SRM/SCM/HCM/QM/XM/WFMCross platformData analysisDatabase management systemsPrinter/Photocopier/ScannereBookeCommercePower Engineering SoftwareDriver assistance systemsFPGAGames industryGaming ClubGraphics software and graphics tabletGraphics card/Video cardSemiconductor technologyHPCICIndustrial RobotInstant Messaging und VoIPInternet of ThingsLinux/UnixMainframeMCU MedicineMicrosoft WindowsMobile Networks Modernization of agricultureMotherboardMusic productionOperating SystemPayment SystemPCI-SIGPLC/DCS/FCS/SCADA/MES Precision Instrument/Medical Equipment/Research EquipmentProduction Engineering/Manufacturing TechnologiesProfessional media softwareProgramming language and frameworkQuantum ComputingRoot name serverSensorSmart phoneSocial networkStreaming MediaStream processorSearch Engine TCP/IP ProtocolsTuring AwardProcessing Units - CPU, GPU, APU, TPU, VPU, FPGA, QPU, IPU, PICVersion controlDistributed systemVirtualization
IT-Times
現場可編程邏輯門陣列 现场可编程逻辑门阵列
Field Programmable Gate Array,FPGA
圖形處理器 图形处理器/graphics processing unit/Grafikprozessor
高带宽存储器
High Bandwidth Memory (engl. kurz: HBM, deutsch Speicher mit hoher Bandbreite) ist eine von AMD zusammen mit SK Hynix entwickeltes breitbandiges Interface, um größere Mengen dynamischen Arbeitsspeichers (8 bis 64 GByte) auf Chipebene mit hoher Übertragungsrate an Grafik- oder Hauptprozessoren anzubinden.
IBM POWER Processor Technology Roadmap
Technology node 7 nm
Launched 2021 Designed by IBM Performance Max. CPU clock rate >5 GHz Cache L2 cache 32 MB per core Architecture and classification Technology node 7 nm Instruction set z/Architecture Physical specifications Cores 8
